1. Field of the Invention
The present invention relates to a method of selectively etching a high impurity concentration semiconductor layer which is provided directly or through a dielectric layer or another layer on a semiconductor substrate in a maufacturing process of a semiconductor device.
2. Description of the Prior Art
In the manufacture of semiconductor devices, a method is known wherein a high impurity concentration semiconductor layer which is provided directly or through a dielectric layer on a semiconductor substrate is selectively removed by an etching solution by utilizing an impurity concentration difference with another semiconductor layer. Such a method has been reported in, for example, Japanese Patent Publication No. 49-36792 and the like.
However, according to such a conventional method, when an element becomes large and micropatterned, uniformity of etching is degraded and a side-etching amount is increased. Particularly, since a temperature of an etching solution is gradually increased, an etching rate becomes different in correspondence with a increase in etching area, giving rise to a significant load effect (charge number dependency). In other words, nonuniformity of etching tends to occur. Since the etching solution has an isotropic property, an etching residue is formed unless over-etching is performed in consideration of irregularities in etching. Then, a side-etching amount becomes undesirably large.